This invention relates to system and a method for improving crosstalk errors such as LSI or PWB (printed wiring board).
As prior-art publications pertinent to the present invention, reference is made to the following publications:
(1) JP Patent Kokai JP-A-7-135457; and
(2) xe2x80x9cCAD of Logic Devicesxe2x80x9d, edited by Kozo Kinoshita, IPSJ(Information Processing Society of Japan), issued Mar. 20, 1981, pages 31 to 62.
If, in the prior-art placing system, the wiring pitch is of a large magnitude, it has been unnecessary to take account of the cross-talk by the neighboring wiring. However, as the wiring becomes finer in pitch with pattern miniaturization, the effect of the crosstalk becomes non-negligible. Thus, after end of the placing and wiring, the cross-talk by the neighboring wiring is calculated to make cross-talk analysis to effect manual correction of the net itself which has caused the crosstalk errors or the wiring pattern of the neighboring net responsible for crosstalk.
Alternatively, the wiring connection designing is manually preliminarily adjusted to preclude an elongated net liable to cause crosstalk errors or superfluous repeater buffers are inserted during logical designing to preclude the occurrence of an unnecessarily long net liable to the effect of crosstalk.
In the wiring designing, automatic wiring means have also been used to suppress occurrence of crosstalk errors for controlling line length for preventing the wiring route of each net from exceeding a pre-set linear length.
However, the above-described techniques suffer from the following drawbacks:
The first drawback is that, after detecting the crosstalk error, the resulting wiring of the net or the neighboring net need to be corrected manually.
The reason is that not only is a large number of manual wiring correction steps required, but also the net to be corrected has a long wiring length itself , so that, depending on the degree of wiring congestion, the wiring correction by itself is insufficient to remove and improve the crosstalk error.
The second drawback is that a manual placing and wiring designing needs to be adjusted preliminarily to eliminate crosstalk errors.
The reason is that a large number of laborious steps are required for the manual placing and wiring operation and the layout (floor plan) needs to be taken into account since the time of logical designing, thus placing limitations on designing to increase designing difficulties to result in a newly increased number of steps.
The third drawback is that excess repeater buffers are inserted during logical designing.
The reason is that the numerous steps required for logical correction and excess repeater buffers worsen the routability or increase the power consumption.
As a fourth drawback there is a problem caused in case where the occurrence of the crosstalk error is suppressed using automatic wiring means which effectuates line length control to prevent the wiring route of each net in the wiring designing from exceeding a pre-set linear wiring length.
That is, since the wiring length of the net itself is long so that, depending on the degree of wiring congestion, there are occasions wherein the limitation on the wiring length alone is insufficient to eliminate or improve the crosstalk error, or the bending or detour of the wiring occurs to the extent more than is necessary to worsen the routability.
It is therefore an object of the present invention to provide a more accurate system and method for improving the crosstalk error whereby the amount of the crosstalk can be calculated only for the net under inspection liable to affect neighboring nets by taking into account the switching timing in detecting the crosstalk errors.
It is another object of the present invention to provide a system and method in which a delay gate is inserted partway on the wiring route of a neighboring affected net or a net on the path to which belongs the neighboring net, among the nets found to be undergoing crosstalk error by the results of layout of usual placing and wiring, to shift the timing to reduce the number of manual correction steps of the crosstalk error for improving the crosstalk error.
A further object of the present invention is as follows: That is, if the crosstalk error is to be improved only by the correction of the wiring route of the net, there are occasions wherein the error cannot be eliminated or improved depending on the degree of the wiring congestion if the wiring length of the net to be corrected is long, whereas, with the method of delaying the timing of the neighboring net by the delay gate, the wiring congested portion can be evaded thus increasing the possibility of improvement in the crosstalk error.
It is also necessary to prevent the routability from being lowered or to prevent the power consumption from being increased as a result of the insertion of excess repeater buffers during logical designing.
It is also necessary to overcome the limitations on the removal and improvement of the crosstalk error in the wiring congestion area and to suppress routability otherwise caused by bending of the wiring to an extent more than is necessary or detour in case of using automatic wiring means controlling the line length to prevent the net wiring route from being placed in excess of a pre-set line length.
There is provided a system for automatically improving and removing the crosstalk error for reducing the number of designing steps.
The switching timing of each net is detected from the results of path delay analysis and crosstalk analysis is carried out so as to take account of the overlap of the switching timing between a net under inspection and a neighboring net. A delay gate insertion unit inserts a delay gate to a neighboring net having timing overlap with the net under inspection undergoing crosstalk error as detected or a net on a path to which belongs the neighboring net. The delay gate inserted is such a delay gate as can improve the crosstalk and as does not cause path delay error. The delay gate inserted by the delay gate placing unit is placed on the route of the net at such a position as can improve the crosstalk error of the net under inspection. An incremental wiring unit re-wires a net divided by the insertion and placing of the delay gate and a net affected by the insertion and placing of the delay gate to improve the crosstalk error automatically.
In an aspect of the present invention, there is provided a crosstalk error improving system comprising:
(a) means for detecting switching timing of each net from the results of path delay analysis to execute crosstalk analysis which takes into account overlap of the switching timing of the net under detection with a neighboring net;
(b) means for inserting a delay gate into a neighboring net having timing overlap with the net under detection undergoing crosstalk error with the net under detection or with a net on a path to which belongs the neighboring net, said delay gate being capable of improving the crosstalk error without causing a path delay error;
(c) means for placing the inserted delay gate at a position on the route of the net capable of improving the crosstalk error of the net under detection; and
(d) means for re-wiring the net divided by the insertion and placing of the delay gate and an affected net.
In a second aspect of the present invention, there is provided a crosstalk error improving system comprising, in a layout designing for LSI or PWB. The system comprises:
(a) logical/library inputting means for inputting:
logical connection information between blocks making up a circuit,
physical information of block placing results and/or inter-block connection wiring results,
delay library information comprising parameters for calculating block internal delay and/or wiring delay required for delay analysis, and
library information for crosstalk analysis comprising parameters for calculating crosstalk magnitude required for crosstalk analysis;
(b) path delay limit value inputting means for inputting path delay time limit value, which comprises minimum delay time limitation and/or maximum delay time limitation, prescribing a target performance of the circuit;
(c) crosstalk magnitude limit value inputting means for inputting a crosstalk magnitude limit value of a net for assuring normal circuit operation;
(d) path delay analysis means for performing delay analysis of all or part of paths;
(e) net switching timing detection means for finding, from the results of the delay analysis, the minimum/maximum time since the clock input time until signal propagation to a net, that is the time during which net switching is likely to occur;
(f) timing overlap detection means for detecting, for all or part of the nets, referred to as xe2x80x9cnet under detectionxe2x80x9d, an overlap of the switching timing between the net under detection and a net having a wiring neighboring to the wiring of the net under detection, referred to as xe2x80x9cneighboring netxe2x80x9d;
(g) crosstalk analysis means for calculating, using the library information for crosstalk analysis, crosstalk magnitude to the net under detection from the neighboring net having timing overlap as detected by the timing overlap detection means, to detect the net subjected to the crosstalk error;
(h) delay gate inserting means for inserting at least one delay gate, into a net under detection undergoing crosstalk error or a net on a path to which belongs the neighboring net having timing overlap with the net under detection so as to eliminate the timing overlap, said delay gate being capable of satisfying the delay time limitations of a path to which belongs the neighboring net for improving the crosstalk error;
(i) delay gate placing means for placing a delay gate, that has been inserted into the neighboring net or in the net on the path to which belongs the neighboring net by the delay gate inserting means, at a position on the route of the real wiring result of the net or at a near-by possible placing position, the position being capable of improving the crosstalk error with the net under detection;
(j) incremental wiring means for making re-wiring of the net divided by the inspection and placing of the delay gate and other nets affected by the insertion and placing of the delay gate;
(k) outputting means for outputting the placing wiring results; and
(l) control means for controlling all of said means.
According to a third aspect, crosstalk error improving system further comprises:
(m) delay buffer placing means for placing the delay gate inserted by said delay gate inserting means at a position capable of improving the crosstalk error in an overlapping manner to allow for placing errors, instead of searching for a near-by possible placing position, even if there exists other block(s) at the intended placing position; and
(n) placing error eliminating means for shifting the placing of the block to eliminate the overlap in case the delay gate placed by said delay gate placing means undergoes a placing error.
In a fourth aspect, the delay gate inserting means (h) comprises means for selecting, inserting, placing and wiring two stages of delay inverter gates as a set instead of said delay gate.
In a fifth aspect, the crosstalk error improving system comprises:
instead of (i) said delay gate placing means and (j) said incremental wiring means, (o) same-direction-switching net detection means for detecting the neighboring net having timing overlap with the net under detection and which is switched at all times in the same direction as the net under detection;
(p) inverter gate inserting means for inserting two inverter gates in the neighboring net detected by said same-direction-switching net gate detection means;
(q) inverter gate placing means for placing the inverter gate, inserted into the neighboring net by the inverter gate inserting means, at the positions representing the starting/end points of the parallel wiring domain with the net under detection on the route of the real wiring results of the net or in the near-by possible placing position; and
(r) incremental re-wiring means for re-wiring the wiring of a net divided by the insertion and placing of said inverter gate and the wiring of other nets affected by the insertion and placing of the inverter gate.
In a sixth aspect, the crosstalk error improving system comprises:
instead of said (q) inverter gate placing means, (qq) inverter gate placing means for placing the inverter gates, inserted into the neighboring net by the inverter gate inserting means, at the positions representing the starting/end points of the parallel wiring domain with the net under detection on the route of the real wiring results of the net or in the near-by possible placing position,
provided that said inverter gate placing means places the inverter gate with an overlap to allow for placing error without searching for a near-by possible placing position even if other blocks are present in the intended placing position; and
(s) placing error eliminating means for shifting the placing of a block for eliminating an overlap if the inverter gate placed by said inverter gate placing means undergoes a placing error.
In the following, preferred embodiments of the present invention are explained. In a preferred form of the present invention, net switching timing detection means (106 of FIG. 1) finds, from the results of the delay analysis by the path delay analysis means (105 of FIG. 1), the switching timing of each net, and timing overlap detection means (107 of FIG. 1) detects, for each net or part of the nets (net under detection), an overlap of the switching timing between the net under detection and any net (or nets) having a wiring neighboring to the wiring of the net under detection (neighboring net or nets). On the other hand, the crosstalk analysis means (108 of FIG. 1) calculates, using the library information for crosstalk analysis, the crosstalk magnitude to the net under detection from the neighboring net having timing overlap as detected by the timing overlap detection means, to detect the net subjected to the crosstalk error; and delay gate insertion means (109 of FIG. 1) inserts at least one delay gate into a net under inspection undergoing crosstalk error or a net on a path to which belongs the neighboring net having timing overlap with the net under inspection so as to eliminate the timing overlap. The delay gate is capable of satisfying the delay time limitations of a path to which belong the neighboring net for improving the crosstalk error. In addition, delay gate placing means (110 of FIG. 1) places a delay gate, that has been inserted into the neighboring net or in the net on the path to which belongs the neighboring net by the delay gate inserting means, at a position on the route of the real wiring result of the net or at a near-by possible placing position, the positions being capable of improving the crosstalk error with the net under inspection. Incremental wiring means (111 of FIG. 1) makes re-wiring of the net divided by the insertion and placing of the delay gate and other nets affected by the insertion and placing of the delay gate (e.g., causing a design rule error such as shorting of wires) for automatically improving the crosstalk error. In the preferred form of the present invention, the above means can be implemented by a program executed on, for example, a computer.
In a preferred second form of the present invention, in case where repeater buffer placing means places the inserted repeater buffer at a position capable of improving the crosstalk error, it places the repeater buffer in an overlapping manner to allow for placing errors, instead of searching for a near-by placing enabling position, even if there exists other block(s) at the intended placing position, and placing error removing means (1511 of FIG. 15) shifts the placing of the block(s) for eliminating the overlap in case the placed repeater buffer undergoes a placing error for enabling the repeater buffer to be placed at an ideal placing position to improve crosstalk error to higher precision.
In a preferred second form of the present invention, when repeater buffer placing means places the inserted repeater buffer at a position capable of improving the crosstalk error, it places the repeater buffer in an overlapping manner to allow for placing errors, instead of searching for a near-by placing enabling position, even if there exists other block(s) at the intended placing position, and placing error removing means (1511 of FIG. 15) shifts the placing of the block for eliminating the overlap in case the placed repeater buffer undergoes a placing error for enabling the repeater buffer to be placed at an ideal placing position to improve crosstalk error to higher precision.
In the preferred third form of the present invention, two stages of delay inverter gates as a set are selected, inserted, placed and wired instead of the delay gate.
That is, the placing of the delay gate/delay inverter gate(s) and the wiring of the related net(s) are made on the basis of the actual placing wiring result taking into account the overlap of the switching timing of the signal and the signal changing direction, thus realizing crosstalk error improvement to high precision.
In a fourth preferred form of the present invention, same-direction-switching net detection means (1808 of FIG. 18) detects, among neighboring nets having timing overlap with the net under inspection, a neighboring net which has timing overlap with the net under inspection and which is switched at all times in the same direction as the net under inspection. Inverter gate inserting means (1810 of FIG. 18) inserts two inverter gates in the neighboring net detected by the same-direction-switching net gate detection means. Inverter gate placing means (1811 of FIG. 18) places the inverter gates, inserted in the neighboring net by the inverter gate inserting means, on the positions representing the starting/end points of a real wiring domain parallel with the net under detection on the route of the real wiring result of the net or in the near-by placeable position. Then incremental wiring means (1812 of FIG. 18) re-wires the wiring of a net divided by the insertion and placing of the inverter gates and the wiring of other nets affected by the insertion and placing of the inverter gates, that is the wiring of other nets subjected to designing rule error such as wiring shorting. This enables the crosstalk to be improved to high precision.
In a fifth preferred form of the present invention, inverter gate placing means lays the inverter gates, inserted in the neighboring nets by the inverter gate inserting means, on the positions representing the starting/end points of the real wiring domain parallel with the net under detection on the route of the real wiring result of the net or in the near-by placeable position. The inverter gate placing means places the inverter gate with an overlap to allow for placing error, without searching for a nearby possible placing position, even if other blocks are present in the intended placing position. The placing error eliminating means shifts the placing of a block for eliminating an overlap if the inverter gates placed by the inverter gate placing means undergo a placing error, thus enabling the crosstalk error to be improved to higher precision.
That is, the placing of the delay gate/delay inverter gates and the wiring of the related net(s) are made on the basis of the actual wiring results taking into account the overlap of the switching timing of the signal and the signal switching direction, thus realizing crosstalk error improvement to high precision.